1. Field of the Invention
The invention relates to data storage in memory cells in a semiconductor memory device, and more particularly to charge retention in a semiconductor memory device which has cell capacitors for storing charge in memory cells and stores data by storing charge.
2. Description of Related Art
A random access memory (hereinafter referred to as a “DRAM”) has been conventionally used as a typical example of a memory device which has a cell capacitor for storing charge in a memory cell. FIG. 15 is a circuit block diagram showing a DRAM 1000 as an example of a semiconductor memory device according to a conventional art. A semiconductor memory device such as the DRAM 1000 is configured such that memory cells C00 to Cnm arranged in a matrix shape are divided into multiple cell blocks B1 to Bk. Each of the cell blocks B1 to Bk has a similar configuration. Hereinafter, the cell block B1 will be described as an example of the cell block. Word lines WL0 to WLn for selecting the memory cells C00 to Cnm by each line address are connected to the memory cells C00 to Cnm. Stored charge in the selected memory cells C00 to Cnm is read out onto bit lines BL0, /BL0 to BLm, /BLm as data transfer passages. The bit lines BL0, /BL0 to BLm, /BLm are connected to sense amplifier circuits (not illustrated) provided in a sense amplifier group 102 and the read-out stored charge is differentially amplified on a bit line pair. In a recent large-capacity DRAM 1000, sense amplifier circuits are generally configured between a ground potential GND and a power supply Viic whose voltage is stepped down by an internal step-down power supply.
The memory cells C00 to Cnm corresponding to the bit line pairs BL0 and /BL0 to BLm and /BLm are paired to constitute a memory cell unit U (see FIG. 17). Each of the bit line pairs BL0 and /BL0 to BLm and /BLm is provided with a sense amplifier circuit. Drivers for driving the word lines WL0 to WLn are configured for each row address as a word driver group 101.
The stored charge retained by the memory cells C00 to Cnm selected by the word lines WL0 to WLn is read out onto the bit lines BL0 to /BLm, and is differentially amplified and read out as data by the sense amplifier circuits, or the stored charge in the memory cells C00 to Cnm is refreshed. Consequently, it is necessary to reset (hereinafter referred to as “equalize”) the bit line pairs BL0 and /BL0 to BLm and /BLm at each access cycle in preparation for the next access. Therefore, the bit line pairs are equalized by a bit line equalization group 106 at the end of access (hereinafter referred to as “at the time of pre-charge”).
At the time of equalization, all bit lines BL0 to /BLm belonging to the cell block B1 are short-circuited with each other by a transistor (not illustrated) provided in the bit line equalization group 106. Then, the bit lines are equalized to a reference voltage VPR by a reference voltage generation circuit 104. The bit line pairs which are differentially amplified by the internal step-down voltage Viic are equalized. Therefore, the voltage of the bit lines becomes Viic/2 and the reference voltage VPR is also set at Viic/2. Since many bit lines BL0 to /BLm exist in the cell block B1, the sum of the parasitic capacitances of all bit lines at the time of equalization has a significant capacitance value. The sum of the parasitic capacitances of all bit lines at the time of equalization is shown as the bit line equalization capacitance CPR in FIG. 15.
On the other hand, the potential of a cell plate CP1 for cell capacitors (C0, C1 in FIG. 17) for storing charge in the memory cells C00 to Cnm is also biased to the reference voltage VCP by the reference voltage generation circuit 104. Since the differentially amplified voltage is the voltage Viic also at this location, the reference voltage VCP is generally set at Viic/2 to minimize an electric field applied to the cell capacitors C0, C1. In other words, the reference voltage output from the reference voltage generation circuit 104 is Viic/2. Since the cell plate CP1 is common to all memory cells C00 to Cnm belonging to the cell block B1, the parasitic capacitance has a significant capacitance value. The sum of the parasitic capacitances is shown as the cell plate parasitic capacitance CCP in FIG. 15.
The reference voltages VPR, VCP are supplied to each of the cell blocks B1 to Bk by lines VPR, VCP through NMOS transistors MPR, MCP. In the large-capacity DRAM 1000, the area where the cell blocks B1 to Bk are arranged is large. Therefore, the total wiring length of each of the feeders (the lines VPR, VCP) are large and parasitic resistances RPR0 to RPRk, RCP0 to RCPk exist on the wiring paths.
The lines VPR, VCP are separated from the reference voltage generation circuit 104 by control signals φPR, φCP supplied to the NMOS transistors MPR, MCP. A bias can be externally applied through test pads PCP, PPR.
In addition, the recent large-capacity DRAM or the like is sometimes configured such that dummy capacitors DC00 to DC1m are interposed between dummy word lines DWL0, DWL1 and the bit lines BL0 to /BLm. Owing to this configuration, the dummy word lines DWL0, DWL1 are simultaneously driven by a dummy word driver group 103 at the time of access and charge is supplied supplementarily to the bit lines BL0 to /BLm by using the capacitive coupling effect by the dummy capacitors DC00 to DC1m, thereby improving the margin of stored charge read out from the memory cells C00 to Cnm. An operation for improving the read-out characteristics with regard to information “1” is called assist 1, and an operation for improving the read-out characteristics with regard to information “0” is called assist 0.
An example of a reference voltage generation circuit 104 is shown in FIG. 16. The reference voltage generation circuit 104 is constituted by a reference voltage generation portion 104B and a reference voltage drive portion 104D. In the reference voltage generation portion 104B, the source terminal of a diode-connection type NMOS transistor M7 connected to power supply voltage VDD through a PMOS transistor M6, and the source terminal of a diode-connection type PMOS transistor M8 connected to a ground potential GND through an NMOS transistor M9 are connected with each other. Owing to this configuration, the drain terminals of the transistors M7, M8 output a constant bias voltage independently of the power supply voltage VDD. This bias voltage is input to the gate terminals of an NMOS transistor M10 and a PMOS transistor M11 constituting the reference voltage drive portion 104D. A connection is made between the source terminals of the transistors M10, M11 to constitute an output terminal. Each of the transistors M10, M11 functions as a source follower to keep the voltage of the output terminal at a reference voltage. Resistance devices R1, R2 may be connected to the output terminal as compensating devices.
FIG. 17 shows the memory cell unit U (see FIG. 15). The memory cell unit U is composed of a pair of memory cells C00, C10. In each of the memory cells C00, C10, cell capacitors C0, C1 are connected to bit lines BL0, /BL0 through NMOS transistors M0, M1 controlled by word lines WL0, WL1. In general, the NMOS transistors M0, M1 are called transfer gates. Stored charge is given and received via the NMOS transistors M0, M1 as the transfer gates between charge storage nodes ST0, ST1 which are terminals on one side of the cell capacitors C0, C1 and the bit lines BL0, /BL0 to store data. The terminals on the other side of the cell capacitors C0, C1 are connected to a common cell plate CP1, and the potential of the cell plate CP1 is biased to the reference voltage VCP by the reference voltage generation circuit 104. Since the potential of the cell plate CP1 is the reference voltage for storing charge in the cell capacitors C0, C1, it is a common potential within the cell block B1, and a significant parasitic capacitance value CCP0 is added. The sum of the parasitic capacitances of all cell blocks B1 to Bk is the cell plate parasitic capacitance CCP shown in FIG. 15.
FIG. 18 is the cross section view of a memory cell C00. Although all memory cells have the same cross section structure, reference numerals are given to the memory cell C00 as an example in FIG. 18. The drain terminal of an NMOS transistor M0 controlled by a word line WL0 is stored charge ST0. The stored charge ST0 constitutes one terminal of a cell capacitor C0. The cell capacitor C0 is configured by arranging a cell plate CP1 via a dielectric film 17. The cell plate CP1 extends rightward and is configured so as to be common to all cell capacitors in the cell block B1 via a cell plate CP1 of a neighbor memory cell. The cell plate CP1 is protected by a PSG film 19 as an upper interlayer film, and is formed on a nitride film 15 between the memory cells. Since a parasitic capacitance component exists between these interlayer films 15, 19, a parasitic capacitance CCP0 is added to the cell plate CP1, and the sum of the parasitic capacitances in the entire DRAM 1000 becomes the cell plate parasitic capacitance CCP.
Each access operation in reading, writing, and refreshing data is performed in the same manner till a differential amplification operation by the sense amplifier circuits. In other words, the storage nodes of the memory cells C00 to Cnm selected by the word lines WL0 to WLn corresponding to row addresses are connected to the bit lines BL0 to /BLm. The stored charge which is read out becomes minute charge on a bit line pair, and is differentially amplified by the sense amplifier circuits. Data is read out or refreshed by the differential amplification. (with regard to a writing operation, data is forced to be inverted by external writing after the differential amplification.)
At this point, the potential of the storage nodes ST0, ST1 of the cell capacitors C0, C1 is sharply fluctuated twice. The first potential fluctuation occurs when the storage nodes ST0, ST1 are connected to the bit lines BL0 to /BLm. Since the bit line capacitance is larger than the cell capacitor capacitance, the stored charge is redistributed when the storage nodes are connected to the bit lines, and the potential of the storage nodes ST0, ST1 is changed from the approximately ground potential GND or the internal step-down voltage Viic to around a bit line equalization voltage VPR (approximately Viic/2). This change is transmitted to the cell plate CP1 through the cell capacitors C0, C1 by capacitive coupling, and the charge is distributed according to the parasitic capacitance of the cell plate CP1 to fluctuate the cell plate potential VCP. However, when the sense amplifier circuits are started and the differential amplification is performed, the bit line potential is restored from Viic/2 to GND or Viic. This potential fluctuation similarly causes the fluctuation in the cell plate potential VCP by the capacitive coupling to the cell plate CP1. These potential fluctuations transmitted by the capacitive coupling are opposite to each other, and are applied in pairs. As a result, the cell plate potential VCP is not fluctuated.
However, there is no stored charge at power-on. In all cell capacitors, no stored charge, or if any, very little stored charge exists. The access operation at this point may cause a problem described in detail below.
The power supply voltage VDD is increased after power-on as shown in FIG. 19. As the power supply voltage VDD is increased, the reference voltage generation circuit 104 starts its operation and the bit line potential VPR and the cell plate potential VCP are increased to Viic/2. At this point, charge is injected from the cell plate potential VCP to the storage nodes ST0, ST1 constituting the cell capacitors C0, C1 by capacitive coupling. Since the injected charge is redistributed to the combined capacitance and gate capacitance of the storage nodes ST0, ST1, the potential VST of the storage nodes ST0, ST1 becomes slightly lower than Viic/2.
When an access operation such as a refresh operation is performed under this condition, the word line WL is activated and the storage nodes ST0, ST1 are connected to the bit lines BL0 to /BLm. At this point, the bit line potential has been equalized to VPR (that is, Viic/2) and almost equals to the potential VST of the storage nodes ST0, ST1, with little charge transferred. Therefore, the storage nodes ST0, ST1 are retained at almost the same potential. When the dummy word line DWL is activated, charge is injected to the bit lines BL0 to /BLm through the dummy capacitors DC00 to DC1m by capacitive coupling. Accordingly, the potential VST of the storage nodes ST0, ST1 becomes slightly higher than Viic/2. When the sense amplifier circuits are started in this potential relationship, the potential VST of the storage nodes ST0, ST1 is increased to the internal step-down voltage Viic level. Owing to this increase in the potential, charge is supplied to the cell plate CP1 through the cell capacitors C0, C1 by capacitive coupling, and the cell plate potential VCP is increased. In a configuration where the dummy word line DWL does not exist, the bit lines BL0 to /BLm are restored to the ground potential GND, and the cell plate potential VCP becomes negative due to capacitive coupling (the detailed description in this regard is omitted). If the directions of the potentials become opposite, an operation similar to the operation described below is performed, and a similar problem arises. The following description relates to the case the cell plate potential VCP is increased when the dummy word line DWL exists.
If the word lines WL0 to WLn are sequentially selected and the above-mentioned operations are repeated before the cell plate potential VCP is restored, the cell plate potential VCP may be increased due to capacitive coupling every time the sense amplifier circuits are activated, and finally it may reach the internal step-down voltage Viic level. The more memory cells among the memory cells C00 to Cnm are restored at one operation, the more noticeably this phenomenon occurs. The typical example is a refresh operation in which more word lines among the word lines WL0 to WLn are selected compared to a normal access operation. Under the circumstances where the capacity of a memory device becomes larger though the capacitance of a cell capacitor cannot be increased, the number of the memory cells among the memory cells C00 to Cnm selected at one operation is increased to maintain a refresh cycle. Therefore, the above-mentioned phenomenon may occur more noticeably as the capacity of a memory device becomes larger in the future. However, the cause of the phenomenon is not limited to the increase in the capacity of a memory device. When each capacitance component depending on the configuration of architecture such as addressing or process technology is distributed in a certain way, the phenomenon may not occur even if the capacity of the memory device is increased. To the contrary, this phenomenon may occur during a normal access operation.
When this phenomenon occurs in the presence of the memory cells C00 to Cnm where the data “0” is written immediately after power-on, charge is supplied also to the storage nodes ST0, ST1 where the data “0” is written from the cell plate CP1 by capacitive coupling as the potential of the cell plate CP1 is increased. Therefore, the potential VST of the storage nodes is increased. When this potential exceeds Viic/2, there arises a problem such as that the data “0” cannot be read out from the memory cells C00 to Cnm, and the data is garbled.
When data 1 is written in the memory cells C00 to Cnm under the condition that the potential of the cell plate CP1 is increased, there may arise a problem that the data disappears because sufficient positive charge is not stored in the charge storage nodes ST0, ST1.
In addition, the cell plate potential VCP may be increased to the internal step-down voltage Viic at the highest. When the data “0” is written after the cell plate potential VCP reaches the internal step-down voltage Viic, excessive electric field stress is applied to the dielectric film 17 (see FIG. 18) between the terminals of the cell capacitors C0, C1. Therefore, there arises a problem that the reliability of the device is adversely affected.
In order to avoid this condition, it is necessary that the reference voltage generation circuit 104 should absorb the charge supplied by capacitive coupling. Therefore, it is conceivable to make the driving capability of the reference voltage generation circuit 104 sufficiently large. However, this measure cannot be realized, because the current consumption in the reference voltage generation circuit 104 is increased and thus the measure contradicts to the demand for a low current consumption operation. In addition, the size of the circuit should be made large. Thus, the measure is difficult to realize also because of the restriction of the chip area.
Since the capacity of a memory device becomes large and thus the number of the arranged memory cells C00 to Cnm becomes large, the area where the cell blocks B1 to Bk are arranged becomes large as described above. The total wiring length of the line VCP becomes large, and the parasitic resistances RCP0 to RCPk on the wiring path are combined with the cell plate parasitic capacitance CCP to form a delay circuit. Therefore, the absorption of the charge generated by capacitive coupling is inhibited despite the increased driving capability of the reference voltage generation circuit 104.